Project Bureau

• Introduction
  • Motivation
  • Supported devices
  • Installation
  • Development
  • Acknowledgements
  • License
• Functional outline (WIP)
• Naming conventions
  • Logic blocks
  • Macrocells
  • Product terms
  • Feedback signals
  • Foldback signals
  • Interconnect switches
  • Global switches
  • Pins, pads, and specials
  • Input signals
  • Input/feedback bus
• Macrocell options (WIP)
  • Overview
  • PT1/PT2 routing group
  • PT3 routing group
  • PT4 routing group
  • PT5 routing group
  • D/Q routing group
  • FB routing group
  • FF/latch configuration
• I/O buffer options
  • Pin termination
  • Output driver type
  • Output slew rate
  • Input hysteresis
  • I/O standards
• Power control options
  • PDx pin multiplexing
  • Input transition detection
  • Reset hysteresis
  • Reducing macrocell power
  • Gating product term power
• Programming options
  • JTAG pin multiplexing
  • Read protection
  • Arming switch
• Database schema
  • General structure
  • Node database
  • Node device['pins']
  • Mapping device['specials']
  • Node device['blocks']
  • Node device['macrocells']
  • Node device['switches']
  • Node device['globals']
  • Node device['config']['pins']
  • Node device['config']
  • Node device['user']
  • Node device['ranges']
• Database explorer
• JTAG programming
  • AS-series programming
  • BE-series programming
• Command-line tools
  • -m util.fuseconv
  • -m util.fusecli