Introduction¶
Project Bureau enables a fully open-source flow for Microchip (Atmel) ATF15xx family CPLDs by documenting their fuse maps and programming algorithms.
You can discuss the project at the IRC channel #prjbureau at libera.chat.
Motivation¶
In 2020, CPLDs are widely considered obsolete. Why, then, work on a CPLD toolchain? Although in applications relying on reconfigurable logic alone, CPLDs are outclassed by FPGAs in every conceivable aspect, they still have advantages in system design: integrated configuration memory, single rail operation, powerful and rugged I/O buffers, and compatibility with 5 V TTL & CMOS systems. It is the last aspect that has motivated the research resulting in Project Bureau.
Although 5 V logic has essentially disappeared from modern digital design, it did not become irrelevant. For decades, the microelectronics industry produced 5 V circuits, many of which are still in use, while others are of historical importance or pursued by retrocomputing enthusiasts. These circuits often use parallel, bidirectional buses, which are challenging to interface with today’s serial, low pin count, low voltage hardware.
Microchip ATF15xx is the last CPLD family in active production that offers true 5 V operation, i.e. rail-to-rail 5 V outputs, providing maximum compatibility with legacy devices. (While some similar devices are still available, such as Lattice ispMACH4A5, they are being phased out, employ 5 V tolerant I/O buffers rather than true 5 V ones, or both.)
Although ATF15xx devices are widely available from distributors, they are not accessible: the proprietary vendor toolchain, developed in late 1990s and last updated in mid-2000s, uses an obscure hardware definition language called CUPL, is Windows-only, requires an expensive programming adapter, and does not properly run on anything newer than Windows XP.
Wouldn’t it be convenient if this CPLD could be used with modern open-source tools like Yosys? Unfortunately, the vendor does not publish information required to develop a toolchain. Fortunately, it isn’t necessary to rely on the vendor here.
Supported devices¶
ATF15xx family devices are currently available in three densities: ATF1502 (32 macrocells), ATF1504 (64 macrocells), and ATF1508 (128 macrocells). Note that ATF1500 is an obsolete device that is, confusingly, not a part of the ATF15xx family.
AS-series (AS, ASV and ASL suffixes) devices, such as ATF1502AS, ATF1504ASV, and ATF1508ASL, are actively produced and widely available. BE-series (BE suffix) devices, such as ATF1502BE, ATF1504BE, and ATF1508BE, are produced on demand and are seldom in stock.
Virtually every aspect of the ATF15xx architecture is well-understood. However, peculiarities of the toolchain result in practical difficulties producing complete fuse map documentation. The following table summarizes the state of the project:
Device(s) |
Fuse database |
Programming |
|---|---|---|
ATF1502AS/ASV/ASL |
Complete |
Complete |
ATF1504AS/ASV/ASL |
Near-complete |
Untested |
ATF1508AS/ASV/ASL |
Partial |
Untested |
ATF1502BE |
Near-complete |
None |
ATF1504BE |
Near-complete |
None |
ATF1508BE |
Partial |
None |
Installation¶
There is nothing to install! Aside from this document, the ultimate artefact of Project Bureau is a single chip database file containing a machine-readable description of every known fuse in every supported device. This file, together with the detailed descriptions from this document, can be used by downstream tooling to produce or manipulate fuse maps. It can also be explored as hypertext.
Development¶
This project provides several utilities for manipulating fuse maps. They require Python 3.6 and the bitarray PyPI package. These utilities are provided for experimental purposes only and are intentionally not packaged; to use them, add this repository to PYTHONPATH:
$ pip3 install bitarray
$ export PYTHONPATH=../path/to/prjbureau
Acknowledgements¶
Although I (whitequark) wrote virtually all of the code and documentation in this project, it would not exist if not for many people in the open FPGA community and beyond. I would like to express my gratitude, in no particular order, to:
Claire Xenia Wolf, for pioneering open FPGA toolchains with Project IceStorm, and inspiring me to start working with programmable logic;
Andrew Zonenberg, for working on gp4par, one of the first open-source place & route tools, and demonstrating clean-room reverse engineering of the interconnect matrix, the most challenging part of a CPLD to document.
I., for assistance in fuzzing the interconnect matrix;
Maya E., for assistance in validating the interconnect routing and minimizing the macrocell truth table, and contributing the JED↔SVF mapping for ATF1504/ATF1508;
Peter Zieba, for bringing the capabilities of the ATF15xx family to my attention, archiving the relevant tools and documentation, and recording high-voltage programming traces;
Myrtle Shah, for building nextpnr-generic, and revealing that place & route tools don’t have to be opaque and arcane;
R. Ou, for working on CPLD synthesis in Yosys, demonstrating a functional CPLD toolchain, and generally ensuring these devices are not forgotten.
License¶
Unless otherwise noted, the files in this repository are covered by the 0-clause BSD license:
Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted.
THE SOFTWARE IS PROVIDED “AS IS” AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.