I/O buffer options

This document describes macrocell input/output buffer options and global input buffer options.

Pin termination

ATF15xx CPLDs provide configurable pull-up/pull-down resistors and bus keeper circuits connected to the pins, collectively called pin termination circuits. Available termination types depend on the series and the pin, though it is always possible to turn termination off.

On ATF15xxAS, the device configuration option config.termination selects the termination (high_z or bus_keeper) for every macrocell at once.

On ATF15xxBE, the macrocell configuration option macrocells[].termination selects the termination (high_z, pull_up, or bus_keeper) individually for each macrocell, and the pin configuration options pins[CLR,CLK1,CLK2,OE1].termination select the termination (high_z, pull_up, pull_down, or bus_keeper) individually for each of the global input pins.

On both series, if the special function of the JTAG pins is selected, the pin configuration options pins[TMS,TDI].termination select the termination (high_z or pull_up) individually for each of the JTAG input pins.

The following table describes the possible termination options:

Series	ATF15xxAS				ATF15xxBE
Pins	Hi-Z	P-Up	P-Dn	Keep	Hi-Z	P-Up	P-Dn	Keep
MCn (global)
MCn (individual)
CLR, CLK1, CLK2, OE1
TMS, TDI1

1

Used when the special function of the pin is selected; otherwise, pin termination is controlled by the macrocell option, if any.

Output driver type

On ATF15xx CPLDs, every macrocell output buffer can be configured as push-pull or open drain (open collector). Setting the macrocell configuration option output_driver to push_pull enables both CMOS transistors in the output driver; setting it to open_drain enables only the NMOS transistor.

Output slew rate

On ATF15xx CPLDs, every macrocell output buffer features individual slew rate control, which may be used to reduce EMI in designs without fast-switching signals. Setting the macrocell configuration option slew_rate to fast selects high strength output drivers for maximum performance; setting it to slow selects low strength output drivers for reducing noise.

Input hysteresis

Portability

This option is present only in BE-series devices.

On ATF15xxBE devices, every macrocell input/output pin and the four global input pins CLR, CLK1, CLK2, OE1 can be configured with or without hysteresis. On these devices, setting the configuration options macrocells[].hysteresis or pins[].hysteresis to on selects the Schmitt trigger input buffer; setting them to off selects the simple CMOS input buffer.

I/O standards

Portability

This option is present only in BE-series devices with 64 macrocells or more.

Normally, ATF15xx CPLD inputs and outputs follow TTL/LVTTL2 or CMOS/LVCMOS3 signaling standards. However, BE-series devices starting with ATF1504BE also support SSTL signaling standards.

On these devices, setting the macrocell configuration option io_standard to sstl (or erasing the device) selects the differential input buffer (referenced to the VREFA or VREFB pins); setting it to lvcmos selects the single-ended CMOS input buffer. Pins for the first half of the macrocells are referenced to VREFA, and for the second half of the macrocells to VREFB. If any pin is referenced to VREFx, then that VREFx pin may only be used for the SSTL reference voltage function.

The following table describes the I/O standards that can be used with different devices and configurations:

Standard	Voltage	ATF15xxAS	ATF15xxASV	ATF1502BE	ATF15xxBE4
TTL output	5 V
TTL input	5 V
CMOS I/O	5 V
LVTTL output	3.3 V
LVTTL input	3.3 V
LVCMOS I/O	3.3 V
SSTL output	3.3 V
SSTL input	3.3 V
LVCMOS I/O	2.5 V
SSTL output	2.5 V
SSTL input	2.5 V
LVCMOS I/O	1.8 V
LVCMOS I/O	1.5 V

2

In TTL and LVTTL, V_IL/V_IH = 0.8/2.0 V and V_OL/V_OH = 0.4/2.4 V.

3

In CMOS and LVCMOS, V_IL/V_IH = 30%/70% Vcc and V_OL/V_OH = 20%/80% Vcc.

4

Other than ATF1502BE.