Changelog
This document describes changes to the public interfaces in the Amaranth language and standard library. It does not include most bug fixes or implementation changes.
Version 0.4 (unreleased)
Support for Python 3.6 has been removed, and support for Python 3.11 has been added.
Features deprecated in version 0.3 have been removed. In particular, the nmigen.* namespace is not provided, # nmigen: annotations are not recognized, and NMIGEN_* envronment variables are not used.
Migrating from version 0.3
Apply the following changes to code written against Amaranth 0.3 to migrate it to version 0.4:
Update shell environment to use
AMARANTH_*environment variables instead ofNMIGEN_*environment variables.Update shell environment to use
AMARANTH_ENV_<TOOLCHAIN>(with all-uppercase<TOOLCHAIN>name) environment variable names instead ofAMARANTH_ENV_<Toolchain>orNMIGEN_ENV_<Toolchain>(with mixed-case<Toolchain>name).
While code that uses the features listed as deprecated below will work in Amaranth 0.4, they will be removed in the next version.
Implemented RFCs
Language changes
Added:
ShapeCastable, similar toValueCastable.Added:
Value.as_signed()andValue.as_unsigned()can be used on left-hand side of assignment (with no difference in behavior).Added:
Const.cast(). (RFC 4)Added:
Value.matches()andwith m.Case():accept any constant-castable objects. (RFC 4)Changed:
Value.cast()castsValueCastableobjects recursively.Changed:
Value.cast()treats instances of classes derived from bothenum.Enumandint(includingenum.IntEnum) as enumerations rather than integers.Changed:
Value.matches()with an empty list of patterns returnsConst(1)rather thanConst(0), to match the behavior ofwith m.Case():.Changed:
Catwarns if an enumeration without an explicitly specified shape is used. (RFC 3)Deprecated:
Const.normalize(). (RFC 5)Removed: (deprecated in 0.1) casting of
Shapeto and from a(width, signed)tuple.Removed: (deprecated in 0.3)
ast.UserValue.Removed: (deprecated in 0.3) support for
# nmigen:linter instructions at the beginning of file.
Standard library changes
Added:
amaranth.lib.enum. (RFC 3)Added:
amaranth.lib.data. (RFC 1)
Toolchain changes
Changed: text files are written with LF line endings on Windows, like on other platforms.
Added:
debug_verilogoverride inbuild.TemplatedPlatform.Deprecated: use of mixed-case toolchain environment variable names, such as
NMIGEN_ENV_DiamondorAMARANTH_ENV_Diamond; use upper-case environment variable names, such asAMARANTH_ENV_DIAMOND.Removed: (deprecated in 0.3)
sim.Simulator.step().Removed: (deprecated in 0.3)
back.pysim.Removed: (deprecated in 0.3) support for invoking
back.rtlil.convert()andback.verilog.convert()without an explicit ports= argument.Removed: (deprecated in 0.3)
test.
Platform integration changes
Added:
OSCHasdefault_clkclock source invendor.lattice_machxo_2_3l.LatticeMachXO2Or3LPlatform.Added: Xray toolchain support in
vendor.xilinx.XilinxPlatform.Removed: (deprecated in 0.3)
lattice_machxo2Removed: (deprecated in 0.3)
lattice_machxo_2_3l.LatticeMachXO2Or3LPlatformSVF programming vector{{name}}.svf.Removed: (deprecated in 0.3)
xilinx_spartan_3_6.XilinxSpartan3APlatform,xilinx_spartan_3_6.XilinxSpartan6Platform,xilinx_7series.Xilinx7SeriesPlatform,xilinx_ultrascale.XilinxUltrascalePlatform.
Version 0.3
The project has been renamed from nMigen to Amaranth.
Features deprecated in version 0.2 have been removed.
Migrating from version 0.2
Apply the following changes to code written against nMigen 0.2 to migrate it to Amaranth 0.3:
Update
import nmigen as nmexplicit prelude imports to beimport amaranth as am, and adjust the code to use theam.*namespace.Update
import nmigen.*imports to beimport amaranth.*.Update
import nmigen_boards.*imports to beimport amaranth_boards.*.Update board definitions using
vendor.lattice_machxo2.LatticeMachXO2Platformto usevendor.lattice_machxo_2_3l.LatticeMachXO2Platform.Update board definitions using
vendor.xilinx_spartan_3_6.XilinxSpartan3APlatform,vendor.xilinx_spartan_3_6.XilinxSpartan6Platform,vendor.xilinx_7series.Xilinx7SeriesPlatform,vendor.xilinx_ultrascale.XilinxUltrascalePlatformto usevendor.xilinx.XilinxPlatform.Switch uses of
hdl.ast.UserValuetoValueCastable; note thatValueCastabledoes not inherit fromValue, and inheriting fromValueis not supported.Switch uses of
back.pysimtosim.Add an explicit
ports=argument to uses ofback.rtlil.convert()andback.verilog.convert()if missing.Remove uses of
test.utils.FHDLTestCaseand vendor the implementation oftest.utils.FHDLTestCase.assertFormalif necessary.
While code that uses the features listed as deprecated below will work in Amaranth 0.3, they will be removed in the next version.
Language changes
Added:
Valuecan be used withabs().Added:
Value.rotate_left()andValue.rotate_right().Added:
Value.shift_left()andValue.shift_right().Added:
ValueCastable.Deprecated:
ast.UserValue; useValueCastableinstead.Added: Division and modulo operators can be used with a negative divisor.
Deprecated:
# nmigen:linter instructions at the beginning of file; use# amaranth:instead.
Standard library changes
Added:
cdc.PulseSynchronizer.Added:
cdc.AsyncFFSynchronizer.Changed:
fifo.AsyncFIFOis reset when the write domain is reset.Added:
fifo.AsyncFIFO.r_rstis asserted when the write domain is reset.Added:
fifo.FIFOInterface.r_levelandfifo.FIFOInterface.w_level.
Toolchain changes
Changed: Backend and simulator reject wires larger than 65536 bits.
Added: Backend emits Yosys enumeration attributes for enumeration-shaped signals.
Added: If a compatible Yosys version is not installed,
back.verilogwill fall back to the amaranth-yosys PyPI package. The package can be installed asamaranth[builtin-yosys]to ensure this dependency is available.Added:
back.cxxrtl.Added:
sim, a simulator interface with support for multiple simulation backends.Deprecated:
back.pysim; usesiminstead.Removed: The
with Simulator(fragment, ...) as sim:form.Removed:
sim.Simulator.add_process()with a generator argument.Deprecated:
sim.Simulator.step(); usesim.Simulator.advance()instead.Added:
build.BuildPlan.execute_remote_ssh().Deprecated:
test.utils.FHDLTestCase, with no replacement.Deprecated:
back.rtlil.convert()andback.verilog.convert()without an explicit ports= argument.Changed: VCD output now uses a top-level “bench” module that contains testbench only signals.
Deprecated:
NMIGEN_*environment variables; useAMARANTH_*environment variables instead.
Platform integration changes
Added:
SB_LFOSCandSB_HFOSCasdefault_clkclock sources inlattice_ice40.LatticeICE40Platform.Added:
lattice_machxo2.LatticeMachXO2Platformgenerates binary (.bit) bitstreams.Deprecated:
lattice_machxo2; uselattice_machxo_2_3l.LatticeMachXO2Platforminstead.Removed:
xilinx_7series.Xilinx7SeriesPlatform.grade; this family has no temperature grades.Removed:
xilinx_ultrascale.XilinxUltrascalePlatform.grade; this family has temperature grade as part of speed grade.Added: Symbiflow toolchain support for
xilinx_7series.Xilinx7SeriesPlatform.Added:
lattice_machxo_2_3l.LatticeMachXO2Or3LPlatformgenerates separate Flash and SRAM SVF programming vectors,{{name}}_flash.svfand{{name}}_sram.svf.Deprecated:
lattice_machxo_2_3l.LatticeMachXO2Or3LPlatformSVF programming vector{{name}}.svf; use{{name}}_flash.svfinstead.Added:
quicklogic.QuicklogicPlatform.Added:
cyclonev_oscillatorasdefault_clkclock source inintel.IntelPlatform.Added:
add_settingsandadd_constraintsoverrides inintel.IntelPlatform.Added:
xilinx.XilinxPlatform.Deprecated:
xilinx_spartan_3_6.XilinxSpartan3APlatform,xilinx_spartan_3_6.XilinxSpartan6Platform,xilinx_7series.Xilinx7SeriesPlatform,xilinx_ultrascale.XilinxUltrascalePlatform; usexilinx.XilinxPlatforminstead.Added: Mistral toolchain support for
intel.IntelPlatform.Added:
synth_design_optsoverride inxilinx.XilinxPlatform.
Versions 0.1, 0.2
No changelog is provided for these versions.
The PyPI packages were published under the nmigen namespace, rather than amaranth.