Project Bureau — ATF1504BE Pinout

Project Bureau aims at documenting the bitstream format of Microchip ATF15xx CPLDs. This is a work in progress. See more in the repository.

Device ATF1504BE is available in packages TQFP100, PQFP100, PLCC84, PLCC68, TQFP44, PLCC44.

Macrocell	Logic Block	Special Function	Device Pad	TQFP100 Pin	PQFP100 Pin	PLCC84 Pin	PLCC68 Pin	TQFP44 Pin	PLCC44 Pin
MC8	A	TDI	M8	4	6	14	12	1	7
MC7	A		M7	6	8	15	—	—	—
MC6	A		M6	8	10	16	13	—	—
MC5	A		M5	9	11	17	14	2	8
MC4	A		M4	10	12	18	15	3	9
MC3	A	PD1, VREFA	M3	12	14	20	17	5	11
MC2	A		M2	13	15	21	—	—	—
MC1	A		M1	14	16	22	18	6	12
MC32	B	TMS	M32	15	17	23	19	7	13
MC31	B		M31	16	18	24	—	—	—
MC30	B		M30	17	19	25	20	8	14
MC29	B		M29	19	21	27	22	—	—
MC28	B		M28	20	22	28	23	—	—
MC27	B		M27	21	23	29	24	—	—
MC26	B		M26	23	25	30	—	—	—
MC25	B		M25	25	27	31	25	10	16
MC24	B		M24	29	31	33	27	11	17
MC23	B		M23	30	32	34	—	—	—
MC22	B		M22	31	33	35	28	—	—
MC21	B		M21	32	34	36	29	12	18
MC20	B		M20	33	35	37	30	13	19
MC19	B		M19	35	37	39	32	14	20
MC18	B		M18	36	38	40	—	—	—
MC17	B		M17	37	39	41	33	15	21
MC33	C		M33	40	42	44	36	18	24
MC34	C		M34	41	43	45	—	—	—
MC35	C	PD2	M35	42	44	46	37	19	25
MC36	C		M36	44	46	48	39	20	26
MC37	C		M37	45	47	49	40	21	27
MC38	C		M38	46	48	50	41	—	—
MC39	C		M39	47	49	51	—	—	—
MC40	C		M40	48	50	52	42	22	28
MC41	C		M41	52	54	54	44	23	29
MC42	C		M42	54	56	55	—	—	—
MC43	C		M43	56	58	56	45	—	—
MC44	C		M44	57	59	57	46	—	—
MC45	C		M45	58	60	58	47	—	—
MC46	C	VREFB	M46	60	62	60	49	25	31
MC47	C		M47	61	63	61	—	—	—
MC48	C	TCK	M48	62	64	62	50	26	32
MC49	D		M49	63	65	63	51	27	33
MC50	D		M50	64	66	64	—	—	—
MC51	D		M51	65	67	65	52	28	34
MC52	D		M52	67	69	67	54	30	36
MC53	D		M53	68	70	68	55	31	37
MC54	D		M54	69	71	69	56	—	—
MC55	D		M55	71	73	70	—	—	—
MC56	D	TDO	M56	73	75	71	57	32	38
MC57	D		M57	75	77	73	59	33	39
MC58	D		M58	76	78	74	—	—	—
MC59	D		M59	79	81	75	60	—	—
MC60	D		M60	80	82	76	61	—	—
MC61	D		M61	81	83	77	62	—	—
MC62	D		M62	83	85	79	64	34	40
MC63	D		M63	84	86	80	—	—	—
MC64	D	CLK3†	M64	85	87	81	65	35	41
—	—	CLK1†	C1	87	89	83	67	37	43
—	—	OE1	E1	88	90	84	68	38	44
—	—	CLR	R	89	91	1	1	39	1
—	—	CLK2†, OE2	C2	90	92	2	2	40	2
MC16	A		M16	92	94	4	4	42	4
MC15	A		M15	93	95	5	—	—	—
MC14	A		M14	94	96	6	5	43	5
MC13	A		M13	96	98	8	7	—	—
MC12	A		M12	97	99	9	8	—	—
MC11	A		M11	98	100	10	9	44	6
MC10	A		M10	99	3	11	—	—	—
MC9	A		M9	100	4	12	10	—	—

† Any of the three on-chip global clock networks GCLK1, GCLK2, and GCLK3 can be driven by any of the three pads with global clock input capability, C1, C2, and M64. The special function names CLK1, CLK2, and CLK3 merely illustrate the typical application.