spi-controller

CLI reference

glasgow run spi-controller

Initiate transactions on the Motorola SPI bus.

usage: glasgow run spi-controller [-h] [-V SPEC] [--cs PIN] [--sck PIN]
                                  [--copi PIN] [--cipo PIN] [-m MODE]
                                  [-f FREQ]
                                  DATA [DATA ...]
data

hex bytes to exchange with the device

-h, --help

show this help message and exit

-V <spec>, --voltage <spec>

configure I/O port voltage to SPEC (e.g.: ‘3.3’, ‘A=5.0,B=3.3’, ‘A=SA’)

--cs <pin>

bind the applet I/O line ‘cs’ to PIN (default: ‘A0’, required)

--sck <pin>

bind the applet I/O line ‘sck’ to PIN (default: ‘A1’, required)

--copi <pin>

bind the applet I/O line ‘copi’ to PIN (default: ‘A2’, optional)

--cipo <pin>

bind the applet I/O line ‘cipo’ to PIN (default: ‘A3’, optional)

-m {0,1,2,3}, --mode {0,1,2,3}

configure active edge and idle state according to MODE (default: 0)

-f <freq>, --frequency <freq>

set SCK frequency to FREQ kHz (default: 100)

API reference

exception glasgow.applet.interface.spi_controller.SPIControllerError
class glasgow.applet.interface.spi_controller.SPIControllerInterface(logger: Logger, assembly: AbstractAssembly, *, cs: GlasgowPin | None = None, sck: GlasgowPin, copi: GlasgowPin | None = None, cipo: GlasgowPin | None = None, mode: Mode | Literal[0, 1, 2, 3] = spi.Mode.IdleLow_SampleRising)
property mode: Mode

SPI mode.

Cannot be changed while a transaction is active.

property clock: ClockDivisor

SCK clock divisor.

select(index=0)

Perform a transaction.

Starting a transaction asserts index-th chip select signal and configures the mode; ending a transaction deasserts the chip select signal. Methods write(), read(), exchange(), and dummy() may be called only while a transaction is active to transfer data on the bus.

For example, to read 16 bytes from an SPI NOR flash at address 0x001234 using the Read (03h) command, use the following code:

iface.mode = 3
async with iface.select():
    await iface.write([0x03])
    await iface.write((0x001234).to_bytes(3, byteorder="big"))
    data = await iface.read(16)

An empty transaction (where the body does not call write(), read(), exchange(), or dummy()) is allowed and causes chip select activity only, in addition to any clock edges required to switch the SPI bus mode with chip select inactive.

Raises:
async exchange(data: Buffer) → memoryview

Exchange data.

Clock data out via the COPI pin while clocking return value in via the CIPO pin.

Raises:

SPIControllerError – If called outside of a transaction.

async write(data: Buffer)

Write data.

Clock data out via the COPI pin.

Raises:

SPIControllerError – If called outside of a transaction.

async read(count: int) → memoryview

Read data.

Clock count bytes in via the CIPO pin.

Raises:

SPIControllerError – If called outside of a transaction.

async dummy(count: int)

Clock dummy cycles.

Clock count dummy cycles. One octet corresponds to 8 dummy cycles.

Warning

The state of COPI pin is undefined during this operation.

Raises:

SPIControllerError – If called outside of a transaction.

async delay_us(duration: int)

Delay operations.

Delays the following SPI bus operations by duration microseconds.

async delay_ms(duration: int)

Delay operations.

Delays the following SPI bus operations by duration milliseconds. Equivalent to delay_us(duration * 1000).

async synchronize()

Synchronization barrier.

Ensures that once this method returns, all previously submitted operations have completed.